Modern integrated circuits, such as microprocessors, utilize clock signals in order to synchronize different parts of the circuits. In order to provide such clock signals, closed-loop circuits such as Delay Locked Loops (DLLs) and Phase Locked Loops (PLLS) are often employed in order to distribute synchronized clock signals. The clock signals outputted by these clocking circuits are typically received by various parts (referred to as receivers) of the integrated circuit to synchronize the operations of such parts.
As input/output (I/O) data rates become increasingly higher reaching, for example, 6.4 GHz or higher in some cases, the data eye for receivers of clock signals is often reduced to about 70 ps due to supply noise, jitter, and frequency dependent attenuation. To reduce data error rate, it is generally preferable that the sampling clocks generated by, for example, DLLs and PLLs be placed at the centers of the data eyes, which require that the phase error of the DLLs and PLLs be zero or close to zero. Unfortunately because of varying frequency and process/voltage/temperature (PVT) conditions, obtaining phase errors of zero or near zero using conventional DLL and PLL designs may be difficult to achieve.